Compensating for analog radio component impairments to relax specifications

ABSTRACT

In order to compensate for performance degradation caused by inferior low-cost analog radio component tolerances of an analog radio, a future system architecture (FSA) wireless communication transceiver employs numerous digital signal processing (DSP) techniques to compensate for deficiencies of such analog components so that modern specifications may be relaxed. Automatic gain control (AGC) functions are provided in the digital domain, so as to provide enhanced phase and amplitude compensation, as well as many other radio frequency (RF) parameters.

CROSS REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims priority from U.S. provisionalapplication No. 60/427,126, filed Nov. 15, 2002, which is incorporatedby reference as if fully set forth.

FIELD OF THE INVENTION

[0002] The present invention generally relates to wireless communicationsystems. More particularly, the present invention relates to digitalsignal processing (DSP) techniques used to compensate for theimpairments introduced in the radio, i.e., filter distortions, phase andamplitude imbalance, power distortions, etc., and variations in thedynamic range of the received signal due to changes in signal strengthand channel loss.

BACKGROUND

[0003] Existing wireless system architectural configurations imposestringent constraints on the system designer with regards to receivingand transmitting communication signals. Moreover, such configurationsoften provide low reliability communication links, high operating costs,and an undesirably low level of integration with other systemcomponents.

[0004] In the radio frequency (RF) section of a conventional low-costwireless transceiver configured with analog components, a considerablelevel of distortion occurs when RF signals are processed. Suchdistortions include filter amplitude and phase nonlinearities, phase andamplitude imbalance, power amplifier nonlinearities, carrier leakage orthe like. Higher cost components with better distortion characteristicsthat enhance signal quality may be overlooked during the design phase inorder to reduce the cost of the end-product.

[0005] In addition, variations in the channel loss and dynamic range ofincoming signals of a wireless communication system must be compensatedfor in an efficient manner without subjecting the signals to unduedistortion or interference.

[0006] Because the costs of components that process RF analog signalsare higher than the components that use (DSP), it is desired to providea digital baseband (DBB) system, including a low cost receiver andtransmitter with low noise and minimal power requirements, that utilizesDSP techniques as much as is practicable.

SUMMARY

[0007] In order to compensate for performance degradation caused byinferior low-cost analog radio component tolerances of an analog radio,a future system architecture (FSA) wireless communication transceiveremploys numerous DSP techniques to compensate for deficiencies of suchanalog components so that modern specifications may be relaxed.Automatic gain control (AGC) functions are provided in the digitaldomain, so as to provide enhanced phase and amplitude compensation, aswell as many other RF parameters.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more detailed understanding of the invention may be had fromthe following description of a preferred example, given by way ofexample and to be understood in conjunction with the accompanyingdrawing wherein:

[0009]FIG. 1 is a block diagram of the receiver side of an FSAtransceiver operating in accordance with the present invention;

[0010]FIG. 2 is a detailed schematic of the analog to digital conversion(ADC) circuit of FIG. 1;

[0011]FIG. 3 shows the individual digital processing modules that areincluded in the receiver DBB compensation processor of FIG. 1;

[0012]FIG. 4 is a block diagram of the transmitter side of the FSAtransceiver operating in accordance with the present invention; and

[0013]FIG. 5 shows the individual digital processing modules that areincluded in the transmitter DBB compensation processor of FIG. 4;

[0014]FIG. 6 shows a preferred configuration of the receiver DBBcompensation modules of FIG. 3; and

[0015]FIG. 7 shows a preferred configuration of the transmitter DBBcompensation modules of FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Described hereinafter is an exemplary embodiment of the inventivefuture system architecture (FSA). FSA is a framework architecture forthe physical layer and RF implementation platforms. FSA enables highperformance solutions to be shifted from RF to digital baseband by usinglow performance radio components and compensating in the DBB for thelower radio performance. Thus, FSA promotes lower cost, lower powerconsumption and lower hardware complexity. By providing crossoptimization between the radio and the DBB, the performance compensationin DBB is tied to the characteristics of the radio that the DBB isintegrated with.

[0017] Preferably, the FSA transceiver disclosed herein is incorporatedinto a wireless transmit/receive unit (WTRU). Hereafter, a WTRU includesbut is not limited to a user equipment, mobile station, fixed or mobilesubscriber unit, pager, or any other type of device capable of operatingin a wireless environment. The features of the FSA transceiver may beincorporated into an integrated circuit (IC) or be configured in acircuit comprising a multitude of interconnecting components.

[0018]FIG. 1 is a block diagram of an FSA receiver subsystem 100 of theFSA transceiver. The FSA receiver subsystem 100 includes an analog radioreceiver 105, analog to digital conversion (ADC) circuit 110, low passfilters (LPFs) 115, 120, receiver DBB compensation processor 125 andcontroller 130. The FSA receiver system provides in-phase (I) andquadrature (Q) outputs 132, 134 after being processed by the receiverDBB compensation processor 125, which are of a higher quality than thequality that analog radio receiver 105 could provide by itself.

[0019] Controller 130 maintains control over all of the activecomponents of analog radio receiver 105, ADC circuit 110, LPFs 115, 120and the receiver DBB compensation processor 125. LPFs 115, 120 may beroot-raised cosine (RRC) filters or other suitable filters. Furthermore,controller 130 has access to transmit power control (TPC) signalsreceived from a base station or other entity via modem 180, wherebycalculations or other functions performed by the controller 130 maydepend. Controller 130 also communicates with a modem 180 and respondsto transmit power control (TPC) signals.

[0020] As shown in FIG. 1, analog radio receiver 105 is a conventionaldirect conversion (DC) receiver which includes an antenna 135 forreceiving wireless signals, a bandpass filter 138, a low noise amplifier(LNA) 140, an optional second filter 145 (e.g., bandpass filter), ademodulator 150 having two outputs 152, 154, a phase-locked loop (PLL)155 and low pass filters (LPFs) 160, 165 for controlling bandwidthselectivity. The PLL generates a local oscillator signal to control thetwo outputs demodulator 150. Output 152 is a quadrature (Q) output ofdemodulator 150 and output 154 is an in-phase (I) output of demodulator150.

[0021] The ADC circuit 110 is connected to the Q and I outputs 152, 154via LPFs 160, 165. In accordance with the present invention, the analogradio receiver 105 is introduced to a digital domain established toenhance the performance characteristics of the analog radio receiver105. The ADC circuit 110 includes two digital gain control circuits 170,175.

[0022] Referring to FIG. 2, each of digital gain control circuits 170,175 include a logarithmic amplifier or other amplifier with knowncompression characteristics 210A, 210B for compressing the input analogsignals received from analog radio receiver 105 from a wider dynamicrange to a lower dynamic range. In other words, the logarithmicamplifiers 210A, 210B apply a particular level of amplification to theinput analog signals in accordance with their amplitude. Digital gaincontrol circuits 170, 175 further include a capacitor 205A, 205B, ADC215A, 215B, look up table (LUT) 220A, 220B and combiner 225A, 225B. TheLUTs 220A, 220B provide an anti-log function used to decompress theconverted digital signals. Capacitors 205A, 205B carry out the functionof a LPF for the purpose of eliminating direct current coupling. Fromthe analog domain, the compression curve of the analog radio receiver iscaptured for future reference. ADCs 215A, 215B digitize the outputs oflogarithmic amplifiers 210A, 210B and provide the digitized outputs toLUTs or anti-log functions 220A, 220B in order to decipher the digitaldomain of the I and Q signals. The outputs of the ADCs 215A, 215B areconverted to a linear scale by generating (2*n−1) bit signals. It may benecessary to add one or more additional gain stages before eachlogarithmic amplifier 210A, 210B if the existing gain is not sufficientto promote saturation. The combiners 225A, 225B combine the digitizedoutputs of LUTs 220A, 220B with sign bits 220A, 220B provided bysaturated outputs of the logarithmic amplifiers 210A, 210B, to generatedigital Q and I outputs 235A, 235B, respectively. The sign bits 220A,220B are created from saturated outputs of logarithmic amplifiers 210A,210B, respectively.

[0023] Digital gain control circuits 170, 175 are used to compensate forchannel loss variation and to support a large dynamic range of incomingsignals (e.g., from 100 dBm to −20 dBm). Digital gain control circuits170, 175 are also used to minimize the number of bits required foroperating the ADCs 215A, 215B and are designed to efficiently compensatefor channel loss variation in an expeditious manner, without distortingthe signal envelope. Digital gain control circuits 170, 175 have alinear response, in dB-per-volt, and in a closed loop system is used tomaintain functions such as stability, settling time, overshoot, etc.

[0024] Referring to FIG. 3, receiver DBB compensation processor 125 isused to enhance the RF performance of the analog radio receiver 105. Thereceiver DBB compensation processor 125 may be implemented usinghardware, a powerful digital signal processor (DSP) and/or software. Thereceiver DBB compensation processor 125 includes:

[0025] 1) Consecutive sample adding module 305;

[0026] 2) High pass filter compensation (HPFC) module 310;

[0027] 3) Normalization compensation module 315 with optional DC offsetfunctionality;

[0028] 4) Time domain compensation module 320;

[0029] 5) Automatic phase imbalance compensation (APIC) module 325;

[0030] 6) Automatic amplitude imbalance compensation (AAIC) module 330;and

[0031] 7) Low noise amplifier (LNA) phase compensation module 335.

[0032] The receiver DBB compensation processor 125 is used to relax RFrequirements of the components in the analog radio receiver 105, andreduce the cost and power consumption of the components used.Impairments due to RF component tolerances are corrected by using alldigital gain control (ADGC) components without a need for adjusting anyof the components in analog radio receiver 105.

[0033] Consecutive sample adding module 305 is used to adjust thebandwidth sampling rate of signals, e.g., 3.84 MHz, received by theanalog radio receiver 105. The consecutive sample adding module 305generates an internal clock that corresponds to the received signals,e.g., 3,840,000 times per second. The requirements for the analog radioreceiver 105 to sample signals at chip rate, e.g., 3.84 million chipsper second. The consecutive sample adding module 305 uses a processingspeed that is at a much higher rate than the chip rate, (e.g., 10 timesthe chip rate), to sample the signals received by analog radio receiver105. Consecutive samples are added on top of each other and a singleoutput is generated, the sampling rate is effectively cut in half,(e.g., five times the chip rate). Thus, the consecutive sample addingmodule 305 reduces the sampling rate. Furthermore, the additional twoconsecutive samples will act as a low pass filter and will provide someselectivity performance on the outer bands of the received signals,allowing the specifications of LPFs 160, 165 to be relaxed. Othermodules that follow the consecutive sample adding module 305 will alsobenefit since they will also be able to operate at the reduced samplingrate.

[0034] The HPFC module 310 is used to compensate for deficiencies ingain of the analog radio receiver 105 whereby consecutive amplifierstages are used to convert received signals from a high frequency to abaseband frequency (e.g., 5 MHz). Direct current (DC) components createdfrom each amplifier stage must be canceled or else the output of theamplifier stages will become saturated. HPF stages are inserted betweenthe amplifier stages in order to allow only AC components to be passedand the DC components to be suppressed. This causes the low pass sectionof the input signal to be altered. Unfortunately, this causes useful lowfrequency components to be suppressed. For example, error magnitudemeasurements (EVM) received in the incoming signals may be suppressed,thus causing impairment of the analog radio receiver 105. The HPFCmodule 310 simulates a reduction in the number poles of the HPF stages(e.g., from 50 KHz to 10 KHz) such that the frequency response of theHPF stages is corrected.

[0035] The normalization compensation module 315 (with optional DCoffset functionality) is used to keep the output power of FSA receiversubsystem 100 constant (i.e., normalized) irrespective of the level ofthe input power received at antenna 135 of the analog radio receiver105. The I and Q signal outputs are normalized using the average powerof the I and Q channel outputs combined over n number of samples.Optionally, direct current (DC) component variations between the I and Qoutputs causes the dynamic range of the FSA receiver subsystem 100 to bereduced using a DC offset function of the normalization compensationmodule 315. The DC offset function essentially provides DC cancellationon each of the I and Q outputs.

[0036] The normalization compensation module 315 also estimates theinput power level of signals received by analog radio receiver 105 andturns on or off the LNA 140, depending on whether the estimated inputpower level falls below a predetermined power level threshold. A slottiming signal may be provided from the modem 180 to the normalizationcompensation module 315, via the controller 130, to aid thenormalization process.

[0037] Time domain compensation module 320 is used to compensate fordeficiencies in the design of LPFs 160, 165 of analog radio receiver105, such as group delay variation which tracks phase variation overfrequency.

[0038] The APIC module 325 is used to compensate for deficiencies in thedesign of demodulator 150 of analog receiver 105, whereby phaseimbalances exist between the I and Q outputs 154 and 152. If the I and Qoutputs are orthogonal to each other where the real and imaginary partshave a phase difference of 90 degrees, then the average (mean) value ofthe product of the I and Q signals for each sample over a particularperiod of time should be zero, as indicated by an internal error signal.If the phase difference between the I and Q signals is not orthogonal,the error signal is not equal to zero, e.g., the error signal ispositive for a phase greater than ninety degrees and negative for aphase difference less than ninety degrees. A negative feedback loopwithin the APIC module 325 is used to adjust the phase of the I and Qsignals, thus causing the error signal to return to zero indicating thatthe I and Q signals are orthogonal.

[0039] The AAIC module 330 is used to compensate for deficiencies in thedesign of demodulator 150 of analog receiver 105, whereby amplitudeimbalances (e.g., instantaneous power differences) exist between the Iand Q outputs 152 and 154. If the magnitude of signals on the I and Qoutputs 152 and 154 are not the same, a gain factor is applied to one ofthe signals such that the magnitude of the I signal is equal to themagnitude to the Q signal. The magnitude of the difference betweenimbalances of the I and Q signals is determined by taking the absolutevalue of I and the absolute value of Q and subtracting one from theother. Gain adjustments are then made so that an error signal generatedwithin the AAIC module 330 becomes zero, again with the use of anegative feedback loop. Thus, the amplitudes of I and Q signals arebalanced.

[0040] The LNA phase compensation module 335 is used to adjust the phaseinsertion due to the switching of LNA 140 so that the modem 180 receivesa seamless data stream.

[0041]FIG. 4 is a block diagram of an FSA transmitter subsystem 400 ofthe FSA transceiver. The FSA transmitter subsystem 400 receives digitalsignals including I and Q components (on its modem side) via inputs 405,410, passes the signals via LPFs 415, 420 and transmitter DBBcompensation processor 425, applies digital to analog conversion (DAC)circuit 430, and applies the analog signals to analog radio transmitter445. DAC circuit 430 includes DACs 435 and 440. FSA transmitter system400 further includes a controller 450 which maintains control over theLPFs 415, 420, transmitter DBB processor 425, the DAC circuit 430 andall of the active components of the analog radio transmitter 445.Furthermore, controller 450 has access to TPC signals received by themodem 180 from a base station or other entity, whereby calculations orother functions performed by the controller 450 may depend. Analog radiotransmitter 445 includes an antenna 455, power amplifier 460, modulator465, power detector 470, temperature sensor 475 and bias current sensor480. The components in the analog radio transmitter consist of low cost(i.e., “low-end” quality) components having “relaxed” specifications.For example, the specifications for the power amplifier need not bestringent because of the availability of a pre-distortion compensationmodule in the transmitter DBB compensation processor 425.

[0042] Referring to FIG. 5, transmitter DBB compensation processor 425includes one or more of the following modules used to enhance theperformance of analog radio transmitter 345:

[0043] 1) Pre-distortion compensation module 505;

[0044] 2) Amplitude imbalance compensation module 510;

[0045] 3) Phase imbalance compensation module 515; and

[0046] 4) DC offset compensation module 520.

[0047] The pre-distortion compensation module 505 is used to correcttransmission amplitude characteristics, such as amplitude modulation(AM) to phase modulation (PM) and PM to AM signal characteristics. Theamplitude and phase characteristics of the power amplifier 460 in theanalog radio transmitter 445 are determined. The pre-distortioncompensation module 505 then looks at the input power level. Based onknown gain and phase characteristics of the power amplifier 460, thepre-distortion compensation module 505 purposely distorts the phase andamplitude of the I and Q signals such that the power amplifier generatesa linear response, rather than a distorted response. The pre-distortioncompensation module 505 may refer to an LUT or the like to obtain suchamplifier characteristics. The advantages of this embodiment of thepresent invention is that standards for parameters such asintermodulation distortion may be met, even though cheap and low qualitycomponents (e.g., an amplifier having a low output power rating) areused in the analog radio transmitter 445.

[0048] Amplitude imbalance compensation module 510 is used to level thesignal inputs I and Q such that the modulator 465 in the analog radiotransmitter 445 modulates the signal inputs I and Q with equal powerlevels. Assuming that the modulator 465 is cheap and of low quality, themodulator 465 is probably prone to amplitude and phase imbalanceproblems. For example, if the I input is 1 dB above the Q signal, themodule 510 will cause the I signal power level to be sent at anamplitude 1 dB lower. Thus, at the output of modulator 465, I and Q willbe at the same amplitude. Using controller 450, I and Q may be turned onand off on an individual basis. For example, if controller 450 turns offthe Q component, whereby only the I component is sent, the controllercan determine what power level the power detector 470 in analog radiotransmitter 445 is reading. Assuming that the power level is a desiredtarget level, the I component is then turned off and the Q component isturned back on. The amplitude imbalance compensation module 510 adjuststhe power level of Q such that the power detector reads the same powerlevel as for signal component I.

[0049] Phase imbalance compensation module 515 is used to adjust thephase of signal inputs I and Q. The power level of the I and Q signalinputs is reduced by 3 dB. It is desired for the I and Q signal outputsto be orthogonal where the real and imaginary parts have a phasedifference of 90 degrees to each other, as indicated by a 3 db increasein power when I and Q are sent together. Based on power level readingsperformed by the power detector 470 of analog radio transmitter 445, aphase difference of less than 90 degrees between I and Q will cause thepower detector to read a power level greater than the target powerlevel. A phase imbalance of greater than 90 degrees of I and Q willcause the power detector to read a power level less than the targetpower.

[0050] DC offset compensation module 520 is used to correct DC problemsassociated with the modulator 465 in analog radio transmitter 445. TheDC level output from the modulator is corrected by shutting off the Iand Q inputs such that their outputs are zero. The DC-offset values forI and Q are determined by sweeping the DC for I and Q sequentially whileobserving the measured minimum detector reading for future reference.

[0051] The compensation modules included in both the receiver DBBcompensation processor 125 and the transmitter DBB compensationprocessor 425 may designed according to numerous configurations. It isanticipated that the normalization compensation module 315 would beneeded in each receiver DBB compensation configuration, whereas othercompensation modules are considered to be optional, depending upon thedeficiencies presented by the analog radio. FIG. 6 shows a preferredexemplary configuration 600 for the modules of the receiver DBBcompensation processor 125, while FIG. 7 shows a preferred exemplaryconfiguration 700 for the modules of the transmitter DBB compensationprocessor 425.

[0052] Upon powering up the FSA transceiver (i.e., WTRU), it isenvisioned that all of the compensation modules would be implemented tooptimize the parameters of the analog radio receiver 105 and analogradio transmitter 445 prior to commencing communications. After thecommencement of communications, selective ones of the compensationmodules may be configured to run on a periodic or continuous basis, orin response to a particular event or user request. For example, if thetemperature sensor 475 in the analog radio transmitter 445 detects arise in temperature of five degrees, activation of one or more of thecompensation modules 505, 510, 515, 520 may be desired.

[0053] The FSA, with the advantageous use of the ADGC, provides DBBimpairment compensation for both transmission and reception, RFselectivity enhancement by the radio resource control (RRC), DC offsetcorrection, crosstalk compensation, HPF compensation, and advancefrequency synthesis and modulation. The inventive FSA is capable ofachieving an instantaneous dynamic range of 70 dB without anyadjustments. Additionally, by using the AGDC an additional 20 dB couldbe obtained by switching the LNA on or off. One significant problem inwideband TDD (WTDD), generalized package radio service (GPRS), enhanceddata rate for global system for mobile communications evolution (EDGE),high speed downlink packet access (HSDPA) is the ability to supportlarge instantaneous power variation, which is easily obtained by thepresent invention. Furthermore, ADGC can be implemented without anyknowledge about the timing of the signal, which is very important incell search, cold acquisition, and initial frequency correction mode. Itis also noted that ADGC as per the present invention providescompensation for fast fading without distorting the signal envelope.

[0054] AGDC offers cost benefits by virtue of its simplicity, and doesnot require any gain control in the radio. ADGC also being an open loopin its nature, introduces neither stability problems nor any overshoot,with no setting time. Most importantly, FSA paves the way for a softwaredefined radio with pronounced advantages.

[0055] While this invention has been particularly shown and describedwith reference to preferred embodiments, it will be understood by thoseskilled in the art that various changes in form and details may be madetherein without departing from the scope of the invention describedhereinabove.

What is claimed is:
 1. A wireless transmit/receive unit (WTRU)comprising: (a) a radio receiver comprising a plurality of analogreceiver components; (b) a radio transmitter comprising a plurality ofanalog transmitter components; (c) at least one controller; and (d) aplurality of compensation modules in communication with the controller,the modules for correcting radio frequency (RF) parameter deficienciesthat exist in at least one of the radio receiver and the radiotransmitter, whereby RF parameter requirements established for one ormore of the analog receiver and transmitter components are relaxed. 2.The WTRU of claim 1 wherein the analog receiver components include atleast one low noise amplifier (LNA) in communication with thecontroller, and one of the modules sends an LNA flag signal to thecontroller to turn on or off the LNA depending upon whether the powerlevel of signals received by the radio receiver fall below apredetermined power level threshold.
 3. The WTRU of claim 1 wherein theanalog transmitter components include at least one power amplifier (PA)having an RF parameter deficiency that fails to meet at least one of theestablished RF parameter requirements, and, based on the characteristicsof the PA, at least one of the modules corrects the RF parameterdeficiency by purposely distorting at least one of phase and amplitudeof signals processed by the PA such that the PA generates a linearresponse rather than a distorted response.
 4. The WTRU of claim 1wherein the analog transmitter components include at least one modulatorhaving an RF parameter deficiency that fails to meet at least one of theestablished RF parameter requirements, and at least one of the modulescorrects the RF parameter deficiency by balancing at least one of phaseand amplitude of signals output from the modulator.
 5. The WTRU of claim4, wherein the modulator has two signal inputs including an in-phase (I)input and a quadrature (Q) input.
 6. The WTRU of claim 1 wherein theanalog transmitter components include at least one modulator having anRF parameter deficiency that fails to meet at least one of theestablished RF parameter requirements, and at least one of the modulescorrects the RF parameter deficiency by compensating for an inaccuratedirect current (DC) offset level output from the modulator.
 7. The WTRUof claim 1 wherein the analog receiver components include at least onelow pass filter (LPF) having an RF parameter deficiency that fails tomeet at least one of the established RF parameter requirements, and atleast one of the modules corrects the RF parameter deficiency byincreasing the sampling rate of signals received by the radio receiver.8. The WTRU of claim 1 wherein the analog receiver components include atleast one amplifier having a gain deficiency that fails to meet at leastone of the established RF parameter requirements, and at least one ofthe modules corrects the gain deficiency by simulating a reduction inthe number of poles of high pass filter (HPF) stages in the amplifier.9. The WTRU of claim 1 wherein at least one of the modules keeps theoutput power of the radio receiver constant irrespective of the level ofinput power received by the radio receiver, and in-phase (I) andquadrature (Q) signal outputs of the receiver are normalized usingaverage power of the signal outputs combined over n number of samples.10. The WTRU of claim 1 wherein the analog receiver components includeat least one low pass filter (LPF) having an RF parameter deficiencythat fails to meet at least one of the established RF parameterrequirements, and at least one of the modules corrects the RF parameterdeficiency by compensating for phase variation over frequency.
 11. TheWTRU of claim 1 wherein the analog receiver components include at leastdemodulator having an RF parameter deficiency that fails to meet atleast one of the established RF parameter requirements, and at least oneof the modules corrects the RF parameter deficiency by balancing atleast one of phase and amplitude of signals output from the modulator.12. The WTRU of claim 1 further comprising: (a) at least one analog todigital (ADC) gain control circuit in communication with the radioreceiver; and (b) at least one low pass filter (LPF) in communicationwith the ADC gain control circuit and at least one of the compensationmodules, wherein the analog receiver components are introduced to adigital domain established to enhance the performance characteristics ofthe radio receiver.
 13. The WTRU of claim 12, wherein the ADC gaincontrol circuit enhances dynamic range of the radio receiver andcompensates for channel loss variation, the ADC gain control circuitcomprising: (i) at least one logarithmic amplifier for compressing thedynamic range of analog signals received from the radio receiver toadjust the dynamic range of the analog signals; (ii) at least one analogto digital converter (ADC) in communication with the logarithmicamplifier, the ADC for digitizing the output of the logarithmicamplifier; and (iii) at least one look up table (LUT) in communicationwith the ADC, wherein the LUT provides anti-logarithmic functionalityand in order to decipher the digital domain output by the ADC.
 14. In awireless system including a radio receiver comprising a plurality ofanalog receiver components and a radio transmitter comprising aplurality of analog transmitter components, a method for enabling radiofrequency (RF) parameter requirements established for one or more of theanalog receiver and transmitter components to be relaxed, the methodcomprising: (a) providing a plurality of RF parameter compensationmodules; (b) detecting the existence of one or more RF parameterdeficiencies that exist in at least one of the radio receiver and radiotransmitter; and (c) allocating one or more of the RF parametercompensation modules to correct the RF parameter deficiencies.
 15. Themethod of claim 14 wherein the analog receiver components include atleast one low noise amplifier (LNA) in communication with thecontroller, and one of the modules sends an LNA flag signal to thecontroller to turn on or off the LNA depending upon whether the powerlevel of signals received by the radio receiver fall below apredetermined power level threshold.
 16. The method of claim 14 whereinthe analog transmitter components includes at least one power amplifier(PA) having an RF parameter deficiency that fails to meet at least oneof the established RF parameter requirements, and, based on thecharacteristics of the PA, at least one of the modules corrects the RFparameter deficiency by purposely distorting at least one of phase andamplitude of signals processed by the PA such that the PA generates alinear response rather than a distorted response.
 17. The method ofclaim 14 wherein the analog transmitter components include at least onemodulator having an RF parameter deficiency that fails to meet at leastone of the established RF parameter requirements, and at least one ofthe modules corrects the RF parameter deficiency by balancing at leastone of phase and amplitude of signals output from the modulator.
 18. Themethod of claim 17, wherein the modulator has two signal inputsincluding an in-phase (I)input and a quadrature (Q) input.
 19. Themethod of claim 14 wherein the analog transmitter components include atleast one modulator having an RF parameter deficiency that fails to meetat least one of the established RF parameter requirements, and at leastone of the modules corrects the RF parameter deficiency by compensatingfor an inaccurate direct current (DC) offset level output from themodulator.
 20. The method of claim 14 wherein the analog receivercomponents include at least one low pass filter (LPF) having an RFparameter deficiency that fails to meet at least one of the establishedRF parameter requirements, and at least one of the modules corrects theRF parameter deficiency by increasing the sampling rate of signalsreceived by the radio receiver.
 21. The method of claim 14 wherein theanalog receiver components include at least one amplifier having a gaindeficiency that fails to meet at least one of the established RFparameter requirements, and at least one of the modules corrects thegain deficiency by simulating a reduction in the number of poles of highpass filter (HPF) stages in the amplifier.
 22. The method of claim 14wherein at least one of the modules keeps the output power of the radioreceiver constant irrespective of the level of input power received bythe radio receiver, and in-phase (I) and quadrature (Q) signal outputsof the receiver are normalized using average power of the signal outputscombined over n number of samples.
 23. The method of claim 14 whereinthe analog receiver components include at least one low pass filter(LPF) having an RF parameter deficiency that fails to meet at least oneof the established RF parameter requirements, and at least one of themodules corrects the RF parameter deficiency by compensating for phasevariation over frequency.
 24. The method of claim 14 wherein the analogreceiver components include at least demodulator having an RF parameterdeficiency that fails to meet at least one of the established RFparameter requirements, and at least one of the modules corrects the RFparameter deficiency by balancing at least one of phase and amplitude ofsignals output from the modulator.
 25. A wireless communications systemcomprising: (a) a radio receiver comprising a plurality of analogreceiver components; (b) a radio transmitter comprising a plurality ofanalog transmitter components; and (c) at least one digital baseband(DBB) compensation processor including a plurality of radio frequency(RF) compensation modules for correcting RF parameter deficiencies thatexist in at least one of the radio receiver and the radio transmitter,whereby RF parameter requirements established for one or more of theanalog receiver and transmitter components are relaxed.
 26. The systemof claim 25 wherein the analog receiver components include at least onelow noise amplifier (LNA), wherein one of the modules sends a signal toturn on or off the LNA depending upon whether the power level of signalsreceived by the radio receiver fall below a predetermined power levelthreshold.
 27. The system of claim 25 wherein the analog transmittercomponents include at least one power amplifier (PA) having an RFparameter deficiency that fails to meet at least one of the establishedRF parameter requirements, and, based on the characteristics of the PA,at least one of the modules corrects the RF parameter deficiency bypurposely distorting at least one of phase and amplitude of signalsprocessed by the PA such that the PA generates a linear response ratherthan a distorted response.
 28. The system of claim 25 wherein the analogtransmitter components include at least one modulator having an RFparameter deficiency that fails to meet at least one of the establishedRF parameter requirements, and at least one of the modules corrects theRF parameter deficiency by balancing at least one of phase and amplitudeof signals output from the modulator.
 29. The system of claim 28,wherein the modulator has two signal inputs including an in-phase(I)input and a quadrature (Q) input.
 30. The system of claim 25 whereinthe analog transmitter components include at least one modulator havingan RF parameter deficiency that fails to meet at least one of theestablished RF parameter requirements, and at least one of the modulescorrects the RF parameter deficiency by compensating for an inaccuratedirect current (DC) offset level output from the modulator.
 31. Thesystem of claim 25 wherein the analog receiver components include atleast one low pass filter (LPF) having an RF parameter deficiency thatfails to meet at least one of the established RF parameter requirements,and at least one of the modules corrects the RF parameter deficiency byincreasing the sampling rate of signals received by the radio receiver.32. The system of claim 25 wherein the analog receiver componentsinclude at least one amplifier having a gain deficiency that fails tomeet at least one of the established RF parameter requirements, and atleast one of the modules corrects the gain deficiency by simulating areduction in the number of poles of high pass filter (HPF) stages in theamplifier.
 33. The system of claim 25 wherein at least one of themodules keeps the output power of the radio receiver constantirrespective of the level of input power received by the radio receiver,and in-phase (I) and quadrature (Q) signal outputs of the receiver arenormalized using average power of the signal outputs combined over nnumber of samples.
 34. The system of claim 25 wherein the analogreceiver components include at least one low pass filter (LPF) having anRF parameter deficiency that fails to meet at least one of theestablished RF parameter requirements, and at least one of the modulescorrects the RF parameter deficiency by compensating for phase variationover frequency.
 35. The system of claim 25 wherein the analog receivercomponents includes at least demodulator having an RF parameterdeficiency that fails to meet at least one of the established RFparameter requirements, and at least one of the modules corrects the RFparameter deficiency by balancing at least one of phase and amplitude ofsignals output from the modulator.
 36. The system of claim 25 furthercomprising: (a) at least one analog to digital (ADC) gain controlcircuit in communication with the radio receiver; and (b) at least onelow pass filter (LPF) in communication with the DBB compensationprocessor and the ADC gain control circuit, wherein the analog receivercomponents are introduced to a digital domain established to enhance theperformance characteristics of the radio receiver.
 37. The system ofclaim 36, wherein the ADC gain control circuit enhances dynamic range ofthe radio receiver and compensates for channel loss variation, the ADCgain control circuit comprising: (i) at least one logarithmic amplifierfor compressing the dynamic range of analog signals received from theradio receiver to adjust the dynamic range of the analog signals; (ii)at least one analog to digital converter (ADC) in communication with thelogarithmic amplifier, the ADC for digitizing the output of thelogarithmic amplifier; and (iii) at least one look up table (LUT) incommunication with the ADC, wherein the LUT provides anti-logarithmicfunctionality and in order to decipher the digital domain output by theADC.
 38. An integrated circuit (IC) for use in a wireless communicationsystem including a radio receiver comprising a plurality of analogreceiver components, and a radio transmitter comprising a plurality ofanalog transmitter components, the IC comprising: (a) at least onecontroller; and (b) a plurality of compensation modules in communicationwith the controller, the modules for correcting radio frequency (RF)parameter deficiencies that exist in at least one of the radio receiverand the radio transmitter, whereby RF parameter requirements establishedfor one or more of the analog receiver and transmitter components arerelaxed.
 39. The IC of claim 38 wherein the analog receiver componentsinclude at least one low noise amplifier (LNA) in communication with thecontroller, and one of the modules sends an LNA flag signal to thecontroller to turn on or off the LNA depending upon whether the powerlevel of signals received by the radio receiver fall below apredetermined power level threshold.
 40. The IC of claim 38 wherein theanalog transmitter components include at least one power amplifier (PA)having an RF parameter deficiency that fails to meet at least one of theestablished RF parameter requirements, and, based on the characteristicsof the PA, at least one of the modules corrects the RF parameterdeficiency by purposely distorting at least one of phase and amplitudeof signals processed by the PA such that the PA generates a linearresponse rather than a distorted response.
 41. The IC of claim 38wherein the analog transmitter components include at least one modulatorhaving an RF parameter deficiency that fails to meet at least one of theestablished RF parameter requirements, and at least one of the modulescorrects the RF parameter deficiency by balancing at least one of phaseand amplitude of signals output from the modulator.
 42. The IC of claim41, wherein the modulator has two signal inputs including an in-phase(I)input and a quadrature (Q) input.
 43. The IC of claim 38 wherein theanalog transmitter components include at least one modulator having anRF parameter deficiency that fails to meet at least one of theestablished RF parameter requirements, and at least one of the modulescorrects the RF parameter deficiency by compensating for an inaccuratedirect current (DC) offset level output from the modulator.
 44. The ICof claim 38 wherein the analog receiver components include at least onelow pass filter (LPF) having an RF parameter deficiency that fails tomeet at least one of the established RF parameter requirements, and atleast one of the modules corrects the RF parameter deficiency byincreasing the sampling rate of signals received by the radio receiver.45. The IC of claim 38 wherein the analog receiver components include atleast one amplifier having a gain deficiency that fails to meet at leastone of the established RF parameter requirements, and at least one ofthe modules corrects the gain deficiency by simulating a reduction inthe number of poles of high pass filter (HPF) stages in the amplifier.46. The IC of claim 38 wherein at least one of the modules keeps theoutput power of the radio receiver constant irrespective of the level ofinput power received by the radio receiver, and in-phase (I) andquadrature (Q) signal outputs of the receiver are normalized usingaverage power of the signal outputs combined over n number of samples.47. The IC of claim 38 wherein the analog receiver components include atleast one low pass filter (LPF) having an RF parameter deficiency thatfails to meet at least one of the established RF parameter requirements,and at least one of the modules corrects the RF parameter deficiency bycompensating for phase variation over frequency.
 48. The IC of claim 38wherein the analog receiver components include at least demodulatorhaving an RF parameter deficiency that fails to meet at least one of theestablished RF parameter requirements, and at least one of the modulescorrects the RF parameter deficiency by balancing at least one of phaseand amplitude of signals output from the modulator.
 49. The IC of claim38 further comprising: (a) at least one analog to digital (ADC) gaincontrol circuit in communication with the radio receiver; and (b) atleast one low pass filter (LPF) in communication with the ADC gaincontrol circuit and at least one of the compensation modules, whereinthe analog receiver components are introduced to a digital domainestablished to enhance the performance characteristics of the radioreceiver.
 50. The IC of claim 49, wherein the ADC gain control circuitenhances dynamic range of the radio receiver and compensates for channelloss variation, the ADC gain control circuit comprising: (i) at leastone logarithmic amplifier for compressing the dynamic range of analogsignals received from the radio receiver to adjust the dynamic range ofthe analog signals; (ii) at least one analog to digital converter (ADC)in communication with the logarithmic amplifier, the ADC for digitizingthe output of the logarithmic amplifier; and (iii) at least one look uptable (LUT) in communication with the ADC, wherein the LUT providesanti-logarithmic functionality and in order to decipher the digitaldomain output by the ADC.